Verification Web Directory.


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Science > Technology > Electronics > CAD > Electronic Design Automation > ASIC Design > Verification

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Home > Science > Technology > Electronics > CAD > Electronic Design Automation > ASIC Design > Verification
Directory of Web Resources @ Expo Central : Verification

Science > Technology > Electronics > CAD > Electronic Design Automation > ASIC Design > Verification : Categories

Science > Technology > Electronics > CAD > Electronic Design Automation > ASIC Design > Verification : Web Resources

Science > Technology > Electronics > CAD > Electronic Design Automation > ASIC Design > Verification : Web-Sites

1. 0-In Design Automation [ Report dead link ]

This company provides functional verification products that help verify multi-million gate ASICs and SOC designs.

http://www.0-in.com/

2. Aptix Corporation [ Report dead link ]

The company develops, manufactures and markets products for designing and verifying complex electronic systems and system-on-chip designs such as digital wireless cellular phones, wireless base stations, network routers, and graphics and multimedia devices.

http://www.aptix.com/

3. Axis Systems [ Report dead link ]

The Company provides EDA tools, products and services to verify functionality of advanced integrated circuits and system-on-chip.

http://www.axiscorp.com/

4. Dynalith Systems [ Report dead link ]

The company provides EDA solutions that enable electronic system designers to verify their algorithms in real hardware environments at an early design stage using C/C++/SystemC.

http://www.dynalith.com/

5. E language Tutorial [ Report dead link ]

An unofficial Specman and E language tutorial including code examples and tips for both beginners and experienced users.

http://www.geocities.com/avidan_e/

6. IKOS Systems [ Report dead link ]

Provides a solution for verifying hardware and software in parallel.

http://www.ikos.com/

7. InnoLogic Symbolic Simulation [ Report dead link ]

ESP is an event driven Verilog symbolic simulator. ESP increases functional coverage and reduces verification runtime. ESP is ideal for memory and block level verification.

http://www.innologic-systems.com